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Ordering number : ENA0653
LC87F7032A
Overview
CMOS IC FROM 32K byte, RAM 1024 byte on-chip
8-bit 1-chip Microcontroller
The LC87F7032A is an 8-bit single chip microcontroller with the following on-chip functional blocks: * CPU: operable at a minimum bus cycle time of 250ns * 32K bytes Flash ROM * On-chip : 1024 bytes * LCD controller/driver * 16bit timer x 2ch + 8bit timer x 1ch or more * Synchronous serial I/O port (with automatic block transmit/receive function) * Asynchronous/synchronous serial I/O port * System clock divider * 20-source 10-vectored interrupt system * 8-bit AD converter x 9-channel * On chip debugger All of the above functions are fabricated on a single chip.
Features
Flash ROM * Block-erasable in 128byte units * 32768 x 8 bits (LC87F7032A) RAM * 1024 x 9-bits (LC87F7032A)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.00
20707HKIM 20061204-S00007 No.A0653-1/21
LC87F7032A
Minimum Bus Cycle Time * 250ns (4MHz) Note: Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) * 750ns (4MHz) Ports * Input/output ports Data direction programmable for each bit individually 12 (P1n, P70 to P73) Data direction programmable in nibble units 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) Other function 3 (DBGP0, DBGP1, DBGP2) * PWM input/output port1 (PWM) * LCD ports Segment output 24 (S00 to S23) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 5 (V1 to V3, CUP1, CUP2) Other functions Input/output ports 8 (PCn) * Oscillator pins 4 (CF1, CF2, XT1, XT2) * Reset pin 1 (RES) * Power supply 4 (VSS1 to 2,VDD1 to 2) 1 (VDC) LCD Controller * Seven display modes are available * Duty 1/3duty, 1/4duty * Bias 1/2bias, 1/3bias * Segment output can be switched to general purpose input/output ports. Timers * Timer 0: 16-bit timer/counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register * Timer1: PWM/16 bit timer/counter with toggle output function Mode 0: 2 channel 8 bit timer/counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as PWM. * Timer4: 8-bit timer with 6-bit prescaler * Timer5: 8-bit timer with 6-bit prescaler * Timer6: 8-bit timer with 6-bit prescaler (with toggle output) * Timer7: 8-bit timer with 6-bit prescaler (with toggle output) * Base Timer 1) The clock signal can be selected from any of the following: Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts of five different time intervals are possible.
No.A0653-2/21
LC87F7032A
SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first is selectable 2) Internal 8 bit baud-rate generator (fastest clock period 4/3 tCYC) 3) Consecutive automatic data communication (1 to 256 bits) * SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) UART * Full duplex * 1 stop bit (2-bit in continuous data transmission) * Built-in baudrate generator AD Converter * 8-bit x 9-channels PWM * Multifrequency 12-bit PWM x 1-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) * Noise rejection function (noise rejection filter's time constant can be selected from 1/32/128 tCYC) Watchdog Timer * Watchdog timer can produce interrupt or system reset. * Watchdog timer has two types. Use an external RC circuit Use the microcontroller's basetimer Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts * 20 sources, 10 vector addresses 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L INT3/base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART-send ADC/T6/T7 Port 0/T4/T5/PWM Interrupt Source
* Priority levels X > H > L * For equal priority levels, vector with lowest address takes precedence.
No.A0653-3/21
LC87F7032A
Subroutine Stack Levels * 512 levels maximum (the stack is allocated in RAM) High-speed Multiplication/Division Instructions * 16-bits x 8-bits (5 tCYC execution time) * 24-bits x 16-bits (12 tCYC execution time) * 16-bits / 8-bits (8 tCYC execution time) * 24-bits / 16-bits (12 tCYC execution time) Oscillation Circuits * On-chip RC oscillation for system clock use. * CF oscillation (4MHz) for system clock use. (Rf built in, Rd external) * Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in, Rd external) * On-chip frequency variable RC oscillation circuit for system clock use. System Clock Divider Function * Low power consumption operation is available * Minimum instruction cycle time (750ns, 1.5s, 3.0s, 6.0s, 12s, 24s, 48s, 96s, 192s can be switched by program (when using 4MHz main clock) Standby Function * HALT mode: HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) Oscillation circuits are not stopped automatically. 2) Released by the system reset or interrupts. * HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1) CF, RC and crystal oscillation circuits stop automatically. 2) Released by any of the following conditions. (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2. (3) Port 0 interrupt * X'tal HOLD mode X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator operation is kept in its state at HOLD mode inception. 3) Released by any of the following conditions (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2. (3) Port 0 interrupt (4) Base-timer interrupt ROM Correct Function * ROM correct program is executed by checking the program counter. * ROM correct program area: 128byte On-chip Debugger Function * Software debug is available on the target board. Package Form * QFP64J(7x7) :Lead-free type * QIP64E(14x14) :Lead-free type Development Tool * On-chip Debugger: TCB87 TypeB+LC87F7032A
No.A0653-4/21
LC87F7032A
Flash ROM Programming boards
Package TQFP64J(7x7) QIP64E(14x14) Programming Boards W87F70256TQ7 W87F70256Q
Package Dimensions
unit : mm (typ) 3289
9.0 7.0 48 49 33 32
7.0
64 1 0.4 (0.5) 0.16 16
17 0.125
1.2max
0.1
(1.0)
SANYO : TQFP64J(7X7)
Package Dimensions
unit : mm (typ) 3159A
17.2 14.0 48 49 33 32
9.0
14.0
64 1 0.8 (1.0)
(2.7)
17 16 0.35 0.15
3.0max
0.1
SANYO : QIP64E(14X14)
17.2
0.8
0.5
No.A0653-5/21
LC87F7032A
Pin Assignment
S23/PC7/RX S22/PC6/TX S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15 S14 S13 S12 S11 S10 S9 S8 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/DBGP0 P06/DBGP1 P07/DBGP2 PWM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LC87F7032A
P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/AN7 P73/INT3/T0IN/AN8 VDD2 VSS2 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH CUP1 CUP2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
S7 S6 S5 S4 S3 S2 S1 S0 COM3 COM2 COM1 COM0 V3 V2 V1 VDC
Top view
SANYO: TQFP64J(7x7) SANYO: QIP64E(14x14)
"Lead-free Type" "Lead-free Type"
No.A0653-6/21
LC87F7032A
System Block Diagram
Interrupt control
IR
PLA
ROM Correct Stand-by control Flash ROM CF RC MRC X'tal Clock generator
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Timer 0 (High-speed clock counter)
Port 1
C register
Timer 1 ALU
Base timer
Port 7
LCD controller
PSW
INT0 to 3 Noise rejection filter
ADC
RAR
Timer 4
RAM
Timer 5
Timer 6
Stack pointer
UART
Timer 7
Watchdog timer
PWM
On-chip debugger
No.A0653-7/21
LC87F7032A
Pin Description
Pin name VSS1,VSS2 VDD1,VDD2 VDC CUP1,CUP2 PWM PORT0 P00 to P07 I/O I/O I/O * Power supply (-) * Power supply (+) * Power supply (+) * Capacitor connecting terminals for step-up/step-down * PWM input/output port * 8bit input/output port * Data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt * Input for AD Converter: AN0(P00) to AN4(P04) * On chip debugger terminal (P05, P06, P07) PORT1 P10 to P17 I/O * 8bit input/output port * Data direction programmable for each bit * Use of pull-up resistor can be specified for each bit individually * Other pin functions P10 SIO0 data output P11 SIO0 data input or bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input or bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/buzzer output PORT7 P70 to P73 I/O * 4bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit individually * Input for AD Converter (AN5 to AN8) * Other functions P70: INT0 input/HOLD release input/timer0L capture input/output for watchdog timer/AN5 P71: INT1 input/HOLD release input/timer0H capture input/AN6 P72: INT2 input/HOLD release input/timer 0 event input/timer0L capture input/AN7 P73: INT3 input (noise rejection filter attached)/timer 0 event input/timer0H capture input/AN8 * Interrupt detection selection Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising and falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Yes Function Option No No No No No Yes
S0 to S15 S16/PC0 to S23/PC7 COM0 to COM3 V1 to V3 RES XT1
O I/O
* Segment output for LCD * Segment output for LCD * Can be used as general purpose input/output port (PC) * UART terminal (S22, S23 )
No No
O I/O I I
* Common output for LCD * LCD output bias power supply * Reset terminal * Input for 32.768kHz crystal oscillation * When not in use, connect to VDD1
No No No No
XT2 CF1 CF2
I/O I O
* Output for 32.768kHz crystal oscillation * When not in use, set to oscillation mode and leave open * Input terminal for ceramic oscillator * When not in use, connect to VDD1 * Output terminal for ceramic oscillator * When not in use, leave open
No No No
No.A0653-8/21
LC87F7032A
Port Output Configuration
Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode.
Terminal P00 to P07 Option applies to: each bit Options 1 2 P10 to P17 each bit 1 2 P70 P71 to P73 S16(PC0) to S23(PC7) each bit None None 1 2 3 CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS CMOS P-ch Open Drain N-ch Open Drain Output Form (Note 1) None Programmable Programmable Programmable Programmable None Pull-up resistor Programmable
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). * 1: Connect as follows to reduce noise on VDD. VSS1 and VSS2 must be connected together and grounded. * 2: The power supply for the internal memory is VDD1. VDD1 and VDD2 are used as the power supply for ports. When VDD1 and VDD2 are not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
Back up capacitors
LSI1 VDD1
Power supply
VDD2 V1 V2 V3 VDC CUP1 CUP2
VSS1 VSS2
No.A0653-9/21
LC87F7032A
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = 0V
Parameter Supply voltage Supply voltage For LCD Symbol VDD max VLCD Pins VDD1,VDD2,V2 V1 V2 V3 Input voltage Input/Output voltage Peak output current Total output current IOAH(2) IOAH(3) IOAH(4) Peak output current IOPL(2) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) Pd max IOPL(1) Port 0 Port 1 Port C Ports 02 to 07 Ports 1, 7, C, PWM Ports 00, 01 Port 7, PWM Port 0 Port 1 Port C TQFP64J(7x7) QIP64E(14 x14) Topr Tstg -20 -55 Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Ta=-20 to +70C Total of all pins Total of all pins Total of all pins Current at each pin IOAH(1) VI VIO(1) IOPH(1) XT1,CF1, RES * Ports 0, 1, 7 * Port C, PWM High level output current Ports 0, 1, 7, C, PWM Port 7, PWM * CMOS output selected * Current at each pin Total of all pins -4 Conditions VDD[V] VDD1=VDD2=V2 min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Specification typ max +4.6 1/2 VDD VDD 3/2 VDD VDD+0.3 VDD+0.3 V unit
-10 -25 -25 -15 6 15 10 35 25 15 185 410 +70 C +125 mW mA
Low level output current
Allowable power dissipation Operating ambient temperature Storage ambient temperature
No.A0653-10/21
LC87F7032A
Recommended Operating Range at Ta = -20C to +70C, VSS1 = VSS2 = 0V
Parameter Operating supply voltage range Supply voltage range in hold mode Input high voltage VIH(2) VIH(3) VIH(4) Input low Voltage VIL(2) VIL(3) VIL(4) Operation cycle time External system clock frequency Oscillation frequency range (Note2-1) FmRC FmCF CF1, CF2 FEXCF(1) CF1 * CF2 open * system clock divider: 1/1 * external clock DUTY=505% 4MHz ceramic resonator oscillation See Fig. 1. RC oscillation target: VDD=3.00V, Ta=25C FsX'tal XT1, XT2 32.768kHz crystal resonator oscillation See Fig. 2. 2.4 to 3.6 32.768 2.4 to 3.6 0.3 0.5 0.7 KHz 2.4 to 3.6 4 2.4 to 3.6 0.1 8 MHz tCYC VIL(1) VIH(1) * Ports 1, 71 to 73 * Port 70 input/interrupt * Ports 0, C * PWM Port 70 Watchdog timer XT1, CF1, RES * Ports 1, 71 to 73 * Port 70 input/interrupt * Ports 0, C * PWM Port 70 Watchdog timer XT1, CF1, RES Output disable Output disable 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 VSS VSS VSS 0.75 0.1 0.2VDD 0.8VDD -1.0 0.25VDD 200 4 s Output disable 2.4 to 3.6 VSS 0.2VDD Output disable Output disable 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 Output disable 2.4 to 3.6 0.3VDD +0.7 0.3VDD +0.7 0.9VDD 0.75VDD VDD VHD VDD1 Symbol VDD(1) VDD(2) Pins VDD1=VDD2=V2 Conditions VDD[V] 0.75stCYC200s 0.75stCYC200s expect on-board write Keep RAM and register data in HOLD mode. 2.2 3.6 min 3.0 2.4 Specification typ max 3.6 3.6 unit
VDD V VDD VDD
Note 2-1: The parts value of oscillation circuit is shown in table 1 and table 2.
No.A0653-11/21
LC87F7032A
Electrical Characteristics at Ta = -20C to +70C, VSS1 = VSS2= 0V
Parameter High level input current Symbol IIH(1) Pins * Ports 0, 1, 7 * Port C, PWM * RES Conditions VDD[V] * Output disabled * Pull-up resister OFF. * VIN=VDD (Including OFF state leak current of the output Tr.) IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 CF1 * Ports 0, 1, 7 * Port C, PWM * RES When configured as an input port VIN=VDD VIN=VDD * Output disabled * Pull-up resister OFF. * VIN=VSS (Including OFF state leak current of the output Tr.) IIL(2) IIL(3) High level output voltage VOH(2) VOH(3) VOH(4) VOH(1) XT1, XT2 CF1 Ports 0, 1, 7 CMOS output option Port C PWM IOH=-0.2mA IOH=-0.1mA IOH=-1.6mA IOH=-0.8mA Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) LCD output voltage regulation VODLC COM0 to COM3 VODLS Port C S0 to S23 P00, P01 Ports 0, 1, 7,PWM IOL=1.6mA IOL=0.8mA IOL=5.0mA IOL=2.5mA IOL=0.1mA IO=0mA V1, V2, V3 LCD level output IO=0mA V1, V2, V3 LCD level output Resistance of pull-up MOS Tr. Hysterisis voltage Pin capacitance VHYS(1) CP * Ports 1, 7 * RES All pins * All other terminals connected to VSS. * f=1MHz * Ta=25C 2.4 to 3.6 10 pF Rpu * Ports 0, 1, 7 VOH=0.9VDD 2.4 to 3.6 2.4 to 3.6 25 50 0.1VDD 200 k V 2.4 to 3.6 0 0.2 When configured as an input port VIN=VSS VIN=VSS IOH=-0.4mA 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 0 -1 -8 VDD -0.4 VDD -0.4 VDD -0.4 VDD -0.4 VDD -0.4 0.4 0.4 0.4 0.4 0.4 0.2 V 2.4 to 3.6 -1 2.4 to 3.6 2.4 to 3.6 1 8 A 2.4 to 3.6 1 min Specification typ max unit
No.A0653-12/21
LC87F7032A
Serial I/O Characteristics at Ta = -20C to +70C, VSS1 = VSS2= 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/ reception mode Serial clock * See Fig. 6. (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/ reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) 2.4 to 3.6 Output Input clock delay time tdD0(2) tdD0(1) SO0(P10), SB0(P11) * Continuous data transmission/ reception mode (Note 4-1-3) * Synchronous 8-bit mode (Note 4-1-3) tdD0(3) (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.05 2.4 to 3.6 2.4 to 3.6 0.03 * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.4 to 3.6 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.4 to 3.6 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.4 to 3.6 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) See Fig. 6. Conditions VDD min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 1tCYC +0.05 s
Serial output
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
Output clock
No.A0653-13/21
LC87F7032A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) 2.4 to 3.6 Output delay Serial output time tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.4 to 3.6 (1/3)tCYC +0.05 0.03 s * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.4 to 3.6 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 2.4 to 3.6 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig. 6. Conditions VDD min 2 2.4 to 3.6 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -20C to +70C, VSS1 = VSS2= 0V
Parameter High/low level pulse width tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(6) Symbol tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72) INT3(P73) (Noise rejection ratio is 1/1.) INT3(P73) (Noise rejection ratio is 1/32.) INT3(P73) (Noise rejection ratio is 1/128.) RES Pins Conditions VDD[V] * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that reset is accepted 2.4 to 3.6 200 s 2.4 to 3.6 256 2.4 to 3.6 64 2.4 to 3.6 2 tCYC 2.4 to 3.6 1 min Specification typ max unit
Serial clock
No.A0653-14/21
LC87F7032A
AD Converter Characteristics at Ta = -20C to +70C, VSS1 = VSS2= 0V
Parameter Resolution Absolute accuracy Conversion time tCAD Symbol N ET Pin/Remarks AN0(P00) to AN4(P04), AN5(P70) to AN8(P73) AD conversion time=32xtCYC (When ADCR2=0) (Note 6-2) AD conversion time 64xtCYC (When ADCR2=1) (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS -1 VAIN 24 (tCYC= 0.75s) 48 (tCYC= 0.75s) VSS (Note 6-1) Conditions VDD[V] min. Specification typ. 8 1.5 320 (tCYC= 10s) 640 (tCYC= 10s) VDD 1 V A s max. unit bit LSB
Note 6-1: The quantization error (1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register.
Consumption Current Characteristics at Ta = -20C to +70C, VSS1 = VSS2= 0V
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pins VDD1= VDD2= V2 Conditions VDD[V] * FmCF=4MHz ceramic resonator oscillation * FmX'tal=32.768kHz crystal oscillation * System clock: CF 4MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 * FmCF=1MHz ceramic resonator oscillation * FmX'tal=32.768kHz crystal oscillation * System clock: CF 1MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 IDDOP(3) * FmCF=0Hz (No oscillation) * FmX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 IDDOP(4) * FmCF=0Hz (No oscillation) * FmX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/2 IDDOP(5) * FmCF=0Hz (No oscillation) * FmX'tal=32.768kHz crystal oscillation * System clock: variable RC oscillation 1MHz * Divider: 1/1 IDDOP(6) * FmCF=0Hz (No oscillation) * FmX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/2 2.4 to 3.6 15 45 A 2.4 to 3.6 20 59 2.4 to 3.6 0.3 0.6 2.4 to 3.6 0.4 0.9 2.4 to 3.6 0.6 1.4 mA 2.4 to 3.6 1.7 4.2 min Specification typ max unit
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A0653-15/21
LC87F7032A
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Pins VDD1= VDD2=V2 HALT mode * FmCF=4MHz Ceramic resonator oscillation * FmX'tal=32.768kHz crystal oscillation * System clock: CF 4MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 IDDHALT(2) HALT mode * FmCF=1MHz Ceramic resonator oscillation * FmX'tal=32.768kHz crystal oscillation * System clock:CF 1MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 IDDHALT(3) HALT mode * FmCF=0Hz(Oscillation stop) * FmX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 IDDHALT(4) HALT mode * FmCF=0Hz(Oscillation stop) * FmX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/2 IDDHALT(5) HALT mode * FmCF=0Hz(Oscillation stop) * FmX'tal=32.768kHz crystal oscillation * System clock: variable RC oscillation 1MHz * Divider: 1/1 IDDHALT(6) HALT mode * FmCF=0Hz(Oscillation stop) * FmX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/2 HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(2) IDDHOLD(1) HOLD mode * CF1=VDD or open (when using external clock) Date/time clock HOLD mode * CF1=VDD or open (when using external clock) * FmX'tal=32.768kHz crystal oscillation 2.4 to 3.6 3.8 24 2.4 to 3.6 0.03 10 2.4 to 3.6 5.5 27 A 2.4 to 3.6 7.5 32 2.4 to 3.6 0.16 0.4 2.4 to 3.6 0.20 0.5 2.4 to 3.6 0.3 1.4 mA 2.4 to 3.6 0.8 2.1 Conditions VDD[V] min Specification typ max unit
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0653-16/21
LC87F7032A
F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2= 0V
Parameter Onboard programming current Programming time tFW(1) * 128-byte programming * Erasing current included * Time for setting up 128-byte data is excluded. 3.0 to 3.6 20 40 ms Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] * 128-byte programming * Erasing current included 3.0 to 3.6 15 40 mA min Specification typ max unit
UART (Full Duplex) Operating Conditions at Ta = +20C to +70C, VSS1 = VSS2= 0V
Parameter Transfer rate Symbol UBR Pin/Remarks UTX(S22), URX(S23) Conditions VDD[V] 2.4 to 3.6 min. 16/3 Specification typ. max. 8192/3 unit tCYC
Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Start bit Start of reception Receive data (LSB first) Stop bit End of reception
UBR
No.A0653-17/21
LC87F7032A
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit parameters Frequency Manufacturer Type Oscillator C1 [pF] 4.00MHz Murata SMD Lead CSTCR4M00G53-R0 CSTLS4M00G53-B0 (15) (15) C2 [pF] (15) (15) Rd1 [] 1k 2.2k Operating supply voltage range [V] 2.4 to 3.6 2.4 to 3.6 Oscillation stabilizing time typ [ms] 0.2 0.2 max [ms] 0.6 0.6 Built in C1, C2 Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 4.)
Subsystem Clock Oscillator Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 2 Subsystem Clock Oscillation Circuit Characteristics Using Crystal Oscillator
Circuit Constant Frequency Manufacturer Oscillator C3 [pF] 32.768kHz Epson Toyocom MC-146 3 C4 [pF] 3 Rf [] Open Rd2 [] 0 Operating supply voltage range [V] 2.4 to 3.6 Oscillation Stabilization Time typ [s] 1 max [s] 3 Applicable CL value=7.0pF Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (See Fig. 4.) Note: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2 Rd1
XT1
XT2
Rf
Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0653-18/21
LC87F7032A
VDD Power supply VDD limit OV Reset time RES
Internal RC Resonator oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution mode
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
Without HOLD Release
HOLD reset signal VALID
Internal RC Resonator oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time Figure 4 Oscillation Stabilizing Time
No.A0653-19/21
LC87F7032A
VDD
RRES
RES CRES
Note: Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (SIO0 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial Input/Output Wave Form
tPIL
tPIH
Figure 7 Pulse Input Timing Condition
No.A0653-20/21
LC87F7032A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice.
PS No.A0653-21/21

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